Trellis: Compressing KV Memory in Transformers

This paper addresses the critical issue of quadratic complexity and memory constraints in Transformers, particularly in long-context applications. By introducing Trellis, a novel architecture that dynamically compresses the Key-Value cache, the authors propose a practical solution to improve efficiency and scalability. The use of a two-pass recurrent compression mechanism and online gradient descent with a forget gate is a key innovation. The demonstrated performance gains, especially with increasing sequence length, suggest significant potential for long-context tasks.