TEMP: A Memory Efficient Physical-aware Tensor Partition-Mapping Framework on Wafer-scale Chips

This article introduces a research paper on a framework called TEMP designed for efficient tensor partitioning and mapping on wafer-scale chips. The focus is on memory efficiency and physical awareness, suggesting optimization for hardware constraints. The target audience is likely researchers and engineers working on large-scale AI models and hardware acceleration.

• •Focus on memory efficiency for large-scale AI models.
• •Addresses physical constraints of wafer-scale chips.
• •Targeted at researchers and engineers in related fields.